The present invention relates to a processing apparatus, and can be suitably used for, for example, a processing apparatus including a plurality of processing units.
One of the techniques for improving the processing performance of a processing apparatus is parallel processing. When parallel processing is implemented in a processing apparatus, for example, a plurality of processing units capable of parallel processing are provided (for example, see Japanese Unexamined Patent Application Publication Nos. 2008-42571 and H05-181817). Techniques disclosed in Japanese Unexamined Patent Application Publication Nos. 2008-42571 and H05-181817 will be described below.
First, the technique disclosed in Japanese Unexamined Patent Application Publication No. 2008-42571 will be described with reference to FIG. 14. FIG. 14 is a diagram showing a block configuration example of a moving picture processing apparatus, which corresponds to the configuration shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2008-42571. The moving picture processing apparatus shown in FIG. 14 includes two moving picture processing units, i.e., a Codec_EL_0 601-0 and a Codec_EL_1 601-1. Each of the Codec_EL_0 601-0 and the Codec_EL_1 601-1 includes a plurality of functional subunits. The configuration shown in FIG. 14 includes a variable length coding unit (VLC) 6010, a frequency transform unit (TRF) 6011, and a motion compensation unit (MC) 6012 as functional subunits. Each of the Codec_EL_0 601-0 and the Codec_EL_1 601-1 further includes a plurality of input/output interfaces (IO: Input-Output) 605 which are respectively connected to the plurality of functional subunits. The Codec_EL_0 601-0 and the Codec_EL_1 601-1 are connected so that they form a ring shape by a ring bus through the input/output interface 605. The input/output interface 605 disposed at a tail-end of the Codec_EL_0 601-0 is connected to the input/output interface 605 disposed at a front-end of the Codec_EL_1 601-1. The moving picture processing apparatus shown in FIG. 14 also includes an LM (Line Memory) 602, a DMAC (Direct Memory Access Controller) 603, and a Mem_Cnt 604. The DMAC 603 is a direct memory access controller that transfers a bit stream to the Codec_EL_0 601-0 and the Codec_EL_1601-1. The Mem_Cnt 604 is a controller that supplies macroblock (MB) data to the Codec_EL_0 601-0 and the Codec_EL_1 601-1. The LM 602 is a line memory that stores, for example, the processing result of the Codec_EL_0 601-0.
Next, the technique disclosed in Japanese Unexamined Patent Application Publication No. H05-181817 will be described with reference to FIG. 15. FIG. 15 is a diagram showing a block configuration example of a parallel processing apparatus, which corresponds to a configuration shown in FIG. 2 of Japanese Unexamined Patent Application Publication No. H05-181817. The parallel processing apparatus shown in FIG. 15 includes a plurality of layers each including a pipelined ring bus 701 that connects a plurality of processing elements (PEs) 700 so that they form a ring shape. The parallel processing apparatus shown in FIG. 15 further includes a packet control device 703 that communicates packets with the PEs 700 in a first row of each layer. The PEs 700 in the second to fourth rows of each layer are sequentially connected to the PEs 700 in the layer immediately below the corresponding layer via a ring bus 702, and have a function of retrieving an output of each PE 700 in the layer above the corresponding layer into the pipelined ring bus 701 of the corresponding layer. The layers are sequentially connected in this manner, thereby allowing packets to flow from a certain pipelined ring bus 701 to another pipelined ring bus 701 without involving the packet control device 703. As a result, the load on the packet control device 703 can be reduced. When queues of the PEs 700 in the first row of a certain layer are congested, it is possible to cause packets to flow from another layer. For example, in the case of causing packets to flow to a PE (3,4), the packet control device 703 can cause packets to flow in a path as indicated by thick arrows, i.e., a path that passes through a PE (3,1), a PE (3,2), a PE (3,3), and the PE (3,4). When queues of the PE (3,1) are congested, the packet control device 703 can cause packets to flow in a path as indicated by thick arrows, i.e., a path that passes through a PE (1,1), a PE (1,2), a PE (2,2), a PE (2,3), the PE (3,3), and the PE (3,4).